Metal-oxide-semiconductor (MOS) capacitors are frequently formed as part of the complementary metal oxide semiconductor (CMOS) process. In a CMOS process, transistors are typically formed by providing an active area with doped source/drain regions in the substrate, a gate insulating layer over the substrate, and a gate electrode over the gate insulating layer. Contacts (e.g., tungsten) connect the source/drain regions and gate electrode with a conductive interconnect structure having several horizontal conductive pattern layers (typically referred to as M1, M2, etc.) and vertical via layers formed within a plurality of inter-metal dielectric (IMD) layers.
For integrating the MOS capacitor fabrication into the same process, the top electrode of the MOS capacitor is formed as part of the gate dielectric layer. The capacitor dielectric is formed as part of the gate insulation layer. The anode contact of the capacitor is formed on the top electrode of the capacitor. A cathode contact connects to the source/drain and bulk substrate.
As transistor dimensions (including gate insulation layer thickness) shrink, leakage becomes a problem, and the gate insulation layer becomes more vulnerable to breakdown. To reduce leakage in advanced, smaller transistors, high-k metal gate structures have been considered. The traditional silicon dioxide gate insulating layer is replaced with a relatively thicker layer of a high-k dielectric material, such as hafnium silicate, zirconium silicate, hafnium dioxide or zirconium dioxide. The polycrystalline silicon gate electrode material is replaced with a metal, such as titanium nitride, tantalum nitride, or aluminum nitride.
Advanced methods of fabricating MOS capacitors, which are compatible with a high-k metal gate process, are desired.